Logic functions are often implemented using a type of integrated circuit known as programmable logic devices (PLDs). These devices can be viewed as logic "templates" which can be easily configured by the manufacturer or consumer to provide custom logic functions not normally offered by IC manufacturers. PLDs typically include a programmable AND (or NAND or OR or NOR) gate array followed by either a programmable or fixed OR (or NOR or XOR) gate array which can be configured to provide a large variety of combinatorial logic functions. Any of several types of flip-flop registers are usually provided on at least some OR array output lines, called sum lines, with feedback lines back into the first array for performing sequential or state machine logic functions.
Among the other integrated logic components on the PLD chip is an architectural feature known as an "output macrocell". An output macrocell is generally defined as a collection of logic elements grouped together and usually associated with an input/output pin whose function is to transfer logic signals from the chip via that pin to other electrical components outside of the chip. One disadvantage of currently available PLDs is that in order to increase performance, some flexibility is sacrificed. Typically, this is done by fixing the number of options available to the user in the output macrocell. On the other hand, efforts to increase flexibility with the addition of optional features have previously sacrificed the high performance of simpler, but less flexible, devices.
FIG. 1 shows one output macrocell 211 of the prior art. The macrocell 211 is connected to a sum line 213 output from an OR gate 215 and to an input/output pin 217. Eight product terms 216 are fixed into a hard-wired OR gate 215. A single flip-flop register 219 is available in the macrocell. Register 219 has clock, preset and clear lines which are each permanently fixed to one input pin or product term for the entire device. Sum line 213 feeds data signals into data input D of register 219, and register 219 stores then outputs the signals, and corresponding inverted signals, through register outputs Q and Q respectively. Sum line 213 also sends combinatorial logic signals from OR gate 215 along a conductor 221. An output select 223 has switching elements O1-O4 which select one of the four output options, combinatorial, inverted-combinatorial, registered and inverted-registered to send to input/output pin 217 along a line 225. The macrocell also has a product term programmable output enable 227 which can select pin 217 for either output or input.
There is only one available feedback line 229 back into programmable AND array 231. A feedback select 233 having switching elements F1-F3 can select the feedback of either the combinatorial state via conductor 235 and switch F1, the register output Q via conductor 237 and switch F2, or the pin input or output via line 239 and switch F3. This limits the user as follows. If pin 217 is selected for input by output enable 227, the input signal follows lines 239 and 229 to AND array 231, thereby precluding the use of the combinatorial output on sum line 213 or the registered outputs Q and Q from flip-flop 219. Even when pin 217 is selected for output, only one of the signals can be fed back into the array 231. The other signal, combinatorial or registered, is not available to the array. This can result in up to half of the chip's resources being sacrificed.
An object of the present invention is to provide programmable logic devices with more flexible output macrocells to permit increased use of the available gates while retaining the high performance of simpler devices.